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Freescale Semiconductor Technical Data
Document Number: MC34700 Rev. 4, 6/2008
9 to 18V, Quad Output, Integrated MOSFET Power Supply
The 34700 is a compact, high efficiency power supply, with on-chip power MOSFETs that feature three step down switching regulators and one low dropout linear regulator. The switching regulators utilize voltage mode control with external compensation, allowing flexibility in optimizing the performance of the 34700 for a given application. The 34700 is ideal for space constrained applications where multiple power rails are required and simplicity of design and implementation of the power supply is necessary. Over-voltage, under-voltage, over-current, and over-temperature protection features ensure robust and reliable operation. Fixed switching frequency, internal soft start, and internal power MOSFETs enable rapid power supply design and development. The 34700 is well suited for power supply designs in wide variety of applications, including set top boxes, cable modems, laser printers, fax machines, point of sale terminals, small appliances, telecom line cards, and DVD players.
34700
POWER SUPPLY
Features
* Three switching regulators: 2 synchronous and 1 non-synchronous * One low dropout linear regulator * Input current capability: * 1.5A continuous on channel 1 * 1.25A continuous on channels 2 and 3 * 400mA continuous on channel 4 * Internal power MOSFETs on all channels * Voltage feed forward on channel 1 * 1.5% Output voltage accuracy on all channels * Cycle-by-cycle current limit and short-circuit protection * Fixed 800kHz switching frequency * Internal soft start * Over-voltage, under-voltage, and over-temperature protection * Open-drain power good output signal * Separate active-high enable input for each channel * Pb-free packaging designated by suffix code EP
VIN1
9V - 18V VIN VDDI VGREG Power Good PGOOD VIN1 VOUT1 VIN2 VIN3 BST1 SW1 COMP1 FB1 BST2 SW2 COMP2 Enable 1 Enable 2 Enable 3 Enable 4 EN1 EN1 EN1 EN_LDO
EP SUFFIX (Pb FREE) 98ASA10800D 32-Pin QFN 5 x 5mm
ORDERING INFORMATION
Device MC34700EP/R2 Temperature Range (TA) -40C to 85C Package 32 QFN
VOUT1 2.0 - 5.25V, 1.5A
VOUT2 0.7 - 3.6V, 1.25A
MC34700
FB2 BST3 SW3 COMP3
VOUT3 0.7 - 3.6V, 1.25A
AGND GND2 GND3
FB3 LDO_VIN LDO
VOUT4 0.7 - 3.6V, 0.4A
LDO_FB
Figure 1. MC34700 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.
(c) Freescale Semiconductor, Inc., 2008. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
Feed Forward
Bootstrap Circuit
BST1 VIN1
VOUT1
Ramp Generator Gate Drive Channel 1 Regulator Control Supervisory Logic
PGOOD
SW1 COMP1 FB1
EN1 EN2 EN3 EN4 EN_LDO
Main System Control Thermal Monitoring Current Monitoring System Reset BandGap Reference Ramp Generator Gate Drive Channel 2 Regulator Control
Bootstrap Circuit
VDDI
0.7V Internal Reference
POR
VGREG VIN LDO_VIN LDO LDO_FB
Channel 3 Regulator Control VG Regulator
Bootstrap Circuit
+ -
Oscillator
Ramp Generator Gate Drive
AGND
Figure 2. 34700 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
+ -
VDDI Internal Regulator
+ -
+ -
BST2 VIN2
SW2
GND2 COMP2 FB2
BST3 VIN3
SW3
GND3 COMP3 FB3
PIN CONNECTIONS
PIN CONNECTIONS
PGOOD
27
32
31
30
29
28
26
VIN1 SW1 SW1 BST1 GND2 SW2 VIN2 BST2
VGREG
25 24 23 22
COMP1
VOUT1
AGND
VDDI
VIN1
FB1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VIN LDO_VIN LDO LDO_FB GND3 SW3 VIN3 BST3
TRANSPARENT TOP VIEW PIN 33
21 20 19 18 17
EN_LDO
FB2
COMP2
FB3
Figure 3. 34700 Pin Connections Table 1. 34700 Pin Definitions
Pin Number 1,32 2,3 4 5 6 7 8 9
Pin Name VIN1 SW1 BST1 GND2 SW2 VIN2 BST2 COMP2
Pin Function Power Input Power Output Input Power Ground Power Output Power Input Input Output
Formal Name DC/DC1 Power Input Switch 1 Output Bootstrap1 Power Ground Switch 2 Output DC/DC2 Power Input Bootstrap2 DC/DC2 Compensation Output DC/DC2 Feedback Input Enable DC/DC1 Enable DC/DC2 Enable DC/DC3 Enable LDO DC/DC3 Feedback Input
COMP3
EN1
EN2
EN3
Definition Buck regulator #1 power input. VIN1 is connected to the drain of DC/ DC1's high side MOSFET. Buck regulator #1 switching node. SW1 is connected to the source of DC/ DC1's high side MOSFET. Bootstrap capacitor input for DC/DC1. Buck regulator #2 power ground. GND2 is connected to the source of DC/ DC2's low side MOSFET. Buck regulator #2 switching node. SW2 is connected to the source of the high side MOSFET and the drain of the low side MOSFET. Buck regulator #2 power input. VIN2 is connected to the drain of DC/ DC2's high side MOSFET. Bootstrap capacitor input for DC/DC2. Buck regulator #2 compensation output. COMP2 is connected to the error amplifiers output. Buck regulator #2's error amplifier inverting input. Connect the output voltage feedback resistor divider and compensation network to this pin. Enables buck regulator #1. Asserting EN1 turns on DC/DC1. Enables buck regulator #2. Asserting EN2 turns on DC/DC2. Enables buck regulator #3. Asserting EN3 turns on DC/DC3. Enables the LDO. Asserting EN_LDO turns on the LDO. Buck regulator #3's error amplifier inverting input. Connect the output voltage feedback resistor divider and compensation network to this pin.
10 11 12 13 14 15
FB2 EN1 EN2 EN3 EN_LDO FB3
Input Input Input Input Input Input
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PIN CONNECTIONS
Table 1. 34700 Pin Definitions (continued)
Pin Number 16
Pin Name
COMP3
Pin Function Output
Formal Name DC/DC3 Compensation Output Bootstrap3 DC/DC3 Power Input Switch 3 Output Power Ground LDO Feedback Input Linear Regulator Output Input supply for the Linear Regulator Input Supply Voltage Gate driver Supply Voltage Output Internal Core Voltage Output Power Good Output Signal Ground VOUT1 Shunt DC/DC1 Feedback Input DC/DC1 Compensation Output Thermal Pad
Definition Buck regulator #3 compensation output. COMP3 is connected to the error amplifiers output. Bootstrap capacitor input for DC/DC3. Buck regulator #3 power input. VIN3 is connected to the drain of DC/ DC3's high side MOSFET. Buck regulator #3 switching node. SW3 is connected to the source of the high side MOSFET and the drain of the low side MOSFET. Buck regulator #3 power ground. GND3 is connected to the source of DC/ DC3's low side MOSFET. The LDO's error amplifier inverting input. Connect the output voltage feedback resistor divider to this pin. LDO output connection. The LDO's power input. LDO_VIN is connected to the drain of the linear regulator's MOSFET. The IC's supply voltage input. Internal regulator used to supply the gate drivers of the buck regulators. Internal regulator used to supply the internal logic and analog blocks. Status signal used to indicate that all the regulators' output voltages are good. Upon a fault occurrence this output goes low. Analog ground of the IC. All signals are referenced to this pin. Buck regulator #1's shunt input. VOUT1 is connected to a discharge MOSFET. Buck regulator #1's error amplifier inverting input. Connect the output voltage feedback resistor divider and compensation network to this pin. Buck regulator #1 compensation output. COMP1 is connected to the error amplifiers output. Thermal pad for heat transfer. Connect the thermal pad to the analog ground and ground plane for heat sinking.
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
BST3
Input Power Input Output Power Ground Input Output Power Input Input Output Output Output Ground Input Input Output
VIN3 SW3 GND3 LDO_FB LDO LDO_VIN VIN VGREG VDDI PGOOD AGND VOUT1 FB1 COMP1
33
GND
Ground
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Input Voltages Input Voltage Input DC/DC1 Voltage, IVin = 0 Input DC/DC 2, 3, and LDO Voltage Switch Node Voltages Switch Node DC/DC1 Switch Node DC/DC2, and 3 Bootstrap Voltages Bootstrap DC/DC1 Bootstrap DC/DC2, and 3 Bootstrap Voltage referenced to Switch Node Voltage Compensation (COMP1, 2, and 3), Feedback (FB1, 2, 3, LDO_FB), VDDI All Other Pins (EN1, 2, 3, EN_LDO, PGOOD, VGREG, LDO, VOUT1) ESD Voltage(1) VBST1 VBST2, VBST3 VBST-VSW VESD 2000 -0.3 to 25 -0.3 to 14 -0.3 to 7.0 -0.3 to 3 -0.3 to 7 V V V VSW1 VSW2, VSW3 -0.3 to 20 -0.3 to 7.0 V VIN VIN1 VIN2, VIN3, VINLDO -0.3 to 20 -0.3 to 20 -0.3 to 7.0 V Symbol Value Unit
V
Human Body Model (HBM) All Pins THERMAL RATINGS Operating Temperature Ambient Junction Peak Package Reflow Temperature During Reflow Storage Temperature THERMAL RESISTANCE Thermal Resistance(2) Junction-to-Case Junction-to-Ambient Power Dissipation TA = 25C TA = 70C TA = 85C TJC TJA PD
(2),(3)
C TA TJ TPPRT TSTG -40 to +85 -40 to +125 300 -40 to +150 C C
C/W 6.7 37 W 2.5 1.3 1.0
Notes 1. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100pF, RZAP = 1500). 2. 3. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 9.0V VIN 18V, - 40C TA 85C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic POWER SUPPLY VIN Voltage Maximum Minimum Standby Current VEN1 = VEN2 = VEN3 = VEN_LDO = 0V Operating Current VEN1 = VEN2 = VEN3 = VEN_LDO = 5.0V, VVIN = 9.0V, Load = 0A Internal Supply Voltage POWER-ON RESET VGREG Rising Threshold Voltage VGREG Falling Threshold Voltage VGREG Hysteresis Voltage VGREG LINEAR REGULATOR On Resistance IVGREG = 80mA Output Voltage BIAS VOLTAGES VGREG Decoupling VGREG = 5V VDDI Decoupling VDDI = 2.5V ENABLE Output Enable Logic High Threshold Voltage VEN1,2,3 VEN_LDO Output Enable Logic Low Threshold Voltage VEN1,2,3 VEN_LDO EN Input Resistance to Ground REFERENCE DC/DC 1, 2, 3 Reference Voltage LDO Reference Voltage VREF1,2,3 VREF_LDO 0.690 0.690 0.700 0.700 0.710 0.710 V V REN_IN 1.5 0.61 M 0.78 V V CVDDI 1.0 CVGREG 1.0 F F VVGREG RVGREGIN 4.75 30 5.25 5.5 V VVGREG_RISE VVGREG_FALL VVGREG_HYS 3.5 3.0 0.2 4.0 3.4 0.55 4.5 4.0 1.0 V V V VDDI IIN 2.3 15.4 2.5 2.7 V ISDB 8.95 15 mA VIN 18 9.0 mA V Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 9.0V VIN 18V, - 40C TA 85C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic POWER GOOD OV Threshold, all regulators Percentage of setpoint UV Threshold, all regulators Percentage of setpoint PGOOD Output Low Level ISINK = 6.0mA BUCK CONVERTER 1 Maximum VIN1 Input Voltage Minimum VIN1 Input Voltage Maximum Output Voltage VIN = 9.0V Minimum Output Voltage VIN = 9.0V Maximum Output Current Total System Accuracy Peak Short-circuit Current Limit High Side On Resistance Equivalent Dropout Resistance VIN1 = 5.5V, VOUT = 3.3V, ILOAD = 2A BUCK CONVERTER 2 Maximum VIN2 Input Voltage Minimum VIN2 Input Voltage Maximum Output Voltage Minimum Output Voltage Maximum Output Current Total System Accuracy Peak Short-circuit Current Limit High Side On Resistance Low Side On Resistance Equivalent Dropout Resistance VIN2 = 1.7V, VOUT = 1.25V, ILOAD = 1.25A SW2 Leakage Current VIN = 12V, VIN2 = 0V, EN2 = 0V ISW2 400 VIN2_MAX VIN2_MIN VDC2VOUTMAX VDC2VOUTMIN IOUTDC2MAX VOUT2 ISHORT2 RDS(ON)_HS RDS(ON)_LS RDO 150 A -1.5 2.0 6.0 1.5 3.6 0.7 1.25 175 150 1.5 4.5 V V V V A % A m m m IOUTDC1MAX VOUT1 ISHORT1 RDS(ON)_HS RDO 183 VDC1VOUTMIN -1.5 2.5 2.0 1.5 150 1.5 4.5 A % A m m VIN1_MAX VIN1_MIN VDC1VOUTMAX 5.25 V 18 9.0 V V V VOL_PGOOD 0.4 UV_TH 92 V OV_TH 108 % % Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 9.0V VIN 18V, - 40C TA 85C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic BUCK CONVERTER 3 Maximum VIN3 Input Voltage Minimum VIN3 Input Voltage Maximum Output Voltage Minimum Output Voltage Maximum Output Current Total System Accuracy Peak Short-circuit Current Limit High Side On Resistance Low Side On Resistance Equivalent Dropout Resistance VIN2 = 1.7V, VOUT = 1.25V, ILOAD = 1.25A SW3 Leakage Current VIN = 12V, VIN3 = 0V, EN3 = 0V LINEAR REGULATOR Maximum LDO Input Voltage Minimum LDO Input Voltage Maximum LDO Output Voltage Minimum LDO Output Voltage Maximum LDO Output Current Total System Accuracy Maximum Dropout Voltage ILDO = 400mA Maximum LDO Power Dissipation Maximum Output Current Minimum Output Current Required Output Decoupling THERMAL SHUTDOWN Maximum Thermal Shutdown Threshold Typical Thermal Shutdown Threshold Minimum Thermal Shutdown Threshold Thermal Shutdown Hysteresis TSD_MAX TSD TSD_MIN TSD_HYS 160 140 120 25 C C C C PDISS_LDO ISHORT_LDO ISHORT_LDO CLDO VINLDOMAX VINLDOMIN VLDOMAX VLDOMIN ILDO VLDO VDROP 250 375 1100 500 10 mW mA mA F -1.5 6.0 1.5 3.6 0.7 400 1.5 V V V V mA % mV ISW3 400 VIN3_MAX VIN3_MIN VDC3VOUTMAX VDC2VOUTMIN IOUTDC3MAX VOUT3 ISHORT3 RDS(ON)_HS RDS(ON)_LS RDO 150 A -1.5 2.0 6.0 1.5 3.6 0.7 1.25 160 140 1.5 4.5 V V V V A % A m m m Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 9.0V VIN 18V, - 40C TA 85C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic OSCILLATOR Switching Frequency VGREG LINEAR REGULATOR Maximum Input dV/dT VIN1 = VIN ENABLE Delay from Enable to Soft Start DC1 Delay from Enable to Soft Start DC2, DC3 SOFT START Soft Start Duration DC1, 2, 3 Soft Start Duration LDO RAMP GENERATORS Ramp Amplitude (DC/DC1) Typical Voltage Range VFF_GAIN1 x VIN1, VIN1 = 18V VFF Gain (DC/DC1) Ramp Amplitude (DC/DC2,3) Typical Voltage Range VFF_GAIN2 x VIN2, VIN2 = 6.0V VFF Gain (DC/DC2,3) Ramp Bottom/Offset (DC/DC1,2,3) Min Duty Cycle (DC/DC1) ILOAD1 = 0A Max Duty Cycle (DC/DC1) ILOAD1 = 0A Min Duty Cycle (DC/DC2,3) ILOAD1 = 0A Max Duty Cycle (DC/DC2,3) ILOAD1 = 0A POWER-GOOD PGOOD Reset Delay PGOOD Glitch Rejection tPG-RESET tPG-FILTER 100 10 s s D2,3 83.6 % D2,3 0 0 % D1 68.4 % VFF_GAIN1 VRAMP_AMP2,
3
Symbol
Min
Typ
Max
Unit
fSW
760
800
840
kHz
VIN_dV/dT 10 -
V/s
tDELAY1 tDELAY2,3
-
1.0 160
-
ms s
tSS_BUCKREG tSS_LDO
2.5 0.3
3.5 0.5
4.5 0.7
ms ms
VRAMP_AMP1 1.0 0.055 -
VP-P V/V VP-P 1.25 0.208 0.2 16 V/V V %
VFF_GAIN2,3 VRAMP_OS D1
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 9.0V VIN 18V, - 40C TA 85C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic BUCK CONVERTER 1 Error Amplifier DC Gain Error Amplifier Unity-gain Bandwidth Error Amplifier Slew Rate @ 15pF Current Limit Timer Current Limit Retry Timeout Period BUCK CONVERTER 2 Error Amplifier DC Gain Error Amplifier Unity-gain Bandwidth Error Amplifier Slew Rate Current Limit Timer Current Limit Retry Timeout Period BUCK CONVERTER 3 Error Amplifier DC Gain Error Amplifier Unity-gain Bandwidth Error Amplifier Slew Rate Current Limit Timer Current Limit Retry Timeout Period LINEAR REGULATOR Current Limit Retry Timeout Period tTIMEOUT_LDO 100 ms AEA GBW SR tLIM3 tTIMEOUT3 110 4.0 1.8 10 100 dB MHz V/s ms ms AEA GBW SR tLIM2 tTIMEOUT2 110 4.0 1.8 10 100 dB MHz V/s ms ms AEA GBW SR tLIM1 tTIMEOUT1 110 4.0 1.8 10 100 dB MHz V/s ms ms Symbol Min Typ Max Unit
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
When products and technologies are first introduced, the power needs are generally met with individual regulators. These regulators can be changed or adjusted to match the ever changing requirements. As products and technologies mature, the requirements become more defined, and the individual regulators can be replaced with a multiple output power IC. The integrated solution is cost effective, and offers size reduction and reliable operation. The 34700 is a high efficiency, four output, integrated power regulator. It includes three switching buck regulators and an LDO. The first buck regulator, DC/DC1, uses a nonsynchronous, voltage mode topology and can operate over a wide external supply voltage range of 9V to 18V. It is capable of delivering 1.5A of continuous current. The other buck regulators, DC/DC 2 and DC/DC3, use a synchronous rectifier, voltage mode topology, and operate from an external supply voltage range of 1.5V to 6V. They are each capable of delivering 1.25A of continuous current. The LDO has a separate input that can be connected to any of the buck regulators' outputs, or to an external supply, depending on the application. The LDO is capable of delivering 400mA of continuous current. The 34700 includes control, supervisory, and protection features. It has individual enables for each regulator. This allows the power up and power down sequencing to be controlled by the user. The 34700 monitors each of the regulators' output voltage for an over-voltage or undervoltage condition. If any of the outputs are out of regulation, either too high or too low, the "power good" status signal will go low. The 34700 includes cycle by cycle current limiting and short-circuit protection, as well as thermal shutdown protection. By integrating the control, supervisory and protection features along with the four regulators into a single 5 x 5mm QFN package, all of the functions that four individual regulators can perform are now available in the 34700.
FUNCTIONAL PIN DESCRIPTION INPUT SUPPLY VOLTAGE (VIN)
IC supply voltage input. This pin should be de-coupled from the VIN1 supply voltage. Filtering is required for proper device operation.
ERROR AMPLIFIER INVERTING INPUT (FB1, FB2, FB3, LDO_FB)
Buck regulator and LDO error amplifier inverting input. Connect the output voltage feedback resistor divider to this pin.
POWER INPUT VOLTAGE (VIN1, VIN2, VIN3, LDO_VIN)
Buck regulators and LDO power input voltage. VIN1, 2, 3 is connected to the drain of the respective DC/DC's high side MOSFET. LDO_VIN is connected to the drain of the linear regulator's pass device. Local bypass capacitors are recommended.
COMPENSATION INPUT (COMP1, COMP2, COMP3)
Buck regulators compensation input. COMP is connected to the error amplifier's output of the respective DC/DC regulator. Connect the external compensation components between the COMP pin and the FB pin of the respective buck regulator.
SWITCH NODE (SW1, SW2, SW3)
Buck regulator's switching node. SW1 is connected to the source of the high side MOSFET. Connect this pin to the cathode of the catch diode and the output inductor. SW2 and SW3 are connected to source of the high side and the drain of the low side MOSFET. Connect this pin to the output inductor.
POWER GROUND (GND2, GND3)
Buck regulator power ground. GND is connected to the source of the low side MOSFET of the respective DC/DC regulator. Connect this pin to the DC/DC regulator's power return path.
ANALOG GROUND (AGND)
Analog ground of the IC. Internal analog and logic signals are referenced to this pin.
BOOTSTRAP INPUT (BST1, BST2, BST3)
Bootstrap capacitor input. Connect a capacitor between the BST and SW pin of the respective DC/DC to enhance the gate of the high side MOSFET during switching.
REGULATOR ENABLE (EN1, EN2, EN3, EN_LDO)
These inputs enable the buck regulators and the LDO. Asserting EN turns on the respective regulator. Control logic remains active as long as VIN is present.
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
VOUT1 SHUNT (VOUT1)
DC/DC1 shunt input. VOUT1 is connected to a discharge MOSFET. This MOSFET is used to discharge the output of DC/DC1 when there is a fault condition, such as thermal shutdown or a short-circuit. It is also used to provide a preload to maintain a minimum duty. Connect this pin to the output of DC/DC1.
drive the gates of the low side MOSFETs of regulators DC/ DC2 and DC/DC3. It is also used to supply the LDO. Connect this pin to a low ESR, 1F bypass capacitor.
INTERNAL SUPPLY VOLTAGE (VDDI)
The internal regulator used to supply the internal logic and analog blocks. VDDI is driven from the gate drive supply voltage, VGREG. Connect this pin to a 1F, low ESR decoupling filter capacitor.
LINEAR REGULATOR OUTPUT (LDO)
LDO regulator output. Connect this pin to the feedback resistor divider and output capacitor.
POWER GOOD OUTPUT SIGNAL (PGOOD)
Status signal used to indicate that all the regulators' output voltages are good. Upon a fault occurrence, this output signal goes low. PGOOD is an open drain output, and must be pulled up by an external resistor to a supply voltage suitable for I/O.
GATE DRIVE SUPPLY VOLTAGE OUTPUT (VGREG)
Internal regulator used to supply the gate drivers. VGREG is driven from the input supply voltage VIN, and is used to
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34700 - Functional Block Diagram Analog Circuitry Power Supplies
VDDI Internal Regulator
Band GAP POR VGREG Logic and Control Enable Inputs (EN1,2,3,LDO) Supervisory Logic Current Monitor Thermal Monitor
DC/DC 1
DC/DC 2
DC/DC 3
LDO
Analog Circuitry
Logic and Control
Power Supplies
Figure 4. Functional Internal Block Diagram
ANALOG CIRCUITRY
VDDI Internal Regulator This internal voltage regulator supplies 2.5V for the internal logic and analog circuitry. VDDI is driven from the gate drive supply voltage, VGREG. Bandgap The internal voltage reference provides the required precision value needed for the on-chip circuitry. This block is driven from the VDDI internal regulator, and generates a highly accurate 0.7V reference voltage for the internal comparators and regulators. POR This internal Power On Reset (POR) monitors the internal voltage regulators (VDDI, VGREG). If the internal regulators are above the specified rising threshold voltage, critical internal blocks are enabled. If the internal supplies are out of regulation, the internal blocks are disabled. VGREG This internal regulator supplies 5V for the gate drivers. VGREG is driven from the input supply voltage VIN, and is
used to drive the gates of the low side MOSFETS of DC/DC 2 and DC/DC3. It is also used to supply the LDO block.
LOGIC AND CONTROL
Enable Inputs (EN1, 2, 3, and EN_LDO) These 4 input control, logic level signals will turn the appropriate voltage regulator outputs on and off. Asserting EN turns on the respective regulator and begins a soft start ramp of the output voltage. Control logic remains active as long as VIN is present. Supervisory Logic This logic function will monitor the internal system control functions, and controls the PGOOD output to signal (logic 0) of any fault occurrence. Conditions monitored include output regulation, over-current, and over-temperature. Current Monitor This block detects over-current in the power MOSFET of each regulator. If an over-current condition is detected the regulator will turn off the MOSFET and wait for a timeout period before attempting a soft start retry.
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Thermal Monitor This block detects the temperature of the device and protects against overheating. If the temperature reaches the thermal shutdown threshold, the regulator will shutdown until the temperature has decreased by the hysteresis.
DC/DC2 This is a synchronous switching buck regulator whose input can be fed from DC/DC1, or an external 1.5V to 6V source. It utilizes voltage mode control with external compensation. It is capable of generating a 0.7V to 3.6V output at 1.25A. DC/DC3
POWER SUPPLIES
DC/DC1 This is a non-synchronous switching buck regulator, utilizing a feed forward voltage mode control, with external compensation. This is the only converter in this IC that will regulate from a wide input supply voltage of 9V to 18V. It is capable of generating a 2V to 5.25V output at 1.5A. This buck regulator is identical to DC/DC2. Note that all three switching regulators switch at 800kHz, and are 120 out of phase to help reduce system noise and input surge currents. LDO This low drop out regulator can feed off of any of the switching regulators or from an external 1.5V to 6V source. The dropout voltage is 250mV at the rated load. It is capable of generating a 0.7V to 3.6V output at 400mA.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Each regulator of the 34700 has three basic modes of operation. open drain after a 100s reset delay. A power good true indicates that all the regulators are functioning in normal operation mode.
NORMAL MODE
In normal mode, the regulator is fully operational. To be in this mode, the 34700 input supply, VIN, needs to be present and within its operating range. The regulator's power input voltage also needs to be present and in range. The ENABLE pin for the regulator needs to be asserted, and the output voltage needs to be in regulation. No over-current or thermal faults are present in normal mode.
PROTECTION FUNCTIONS
The 34700 monitors the regulators for several fault conditions to protect both the system load and the IC from overstress. The response of the 34700 to a fault condition is described as follows.
OUTPUT OVER-VOLTAGE
An over-voltage (OV) condition occurs when the output voltage exceeds the over-voltage threshold, OV_TH. This can occur if the regulator's output is shorted to a supply with a higher output voltage. In this case, the power good signal is pulled low, alerting the host that a fault is present, but the regulator remains active. The regulator will continue to try to regulate the output: DC/DC1 will pulse skip; DC/DC2, 3 will go to minimum duty; and the LDO pass device will go high impedance. To avoid false trips of the OV monitor, the power good circuit has a 10s glitch filter. Once the output voltage falls below the OV threshold and back into regulation, the fault is cleared and the power good signal goes high.
STANDBY MODE
In standby mode, the ENABLE pin for the regulator is held low and the regulator is disabled. VIN needs to be present and within its operating range. The regulator's power input is not needed in this mode, but needs to be present and stable before transitioning to normal mode. The power good signal is low since the regulator's output is disabled. Note that the standby mode consumes the least amount of power.
FAULT MODE
In fault mode, the output is no longer in regulation, or an over-current or a thermal fault is present. To be in this mode the 34700 input supply, VIN needs to be present and within its operating range. The regulator's power input voltage also needs to be present and in range. However, if the power input is outside the operating range, a regulation fault may occur. The ENABLE pin for the regulator needs to be asserted and the power good signal is low.
OUTPUT UNDER-VOLTAGE
An under-voltage (UV) condition occurs when the output voltage falls below the under-voltage threshold, UV_TH. This can occur if the regulator's output is shorted to ground, overloaded, or the power input voltage has decreased. In this case, the power good signal is pulled low, alerting the host that a fault is present, but the regulator remains active. The regulator will continue to try to regulate the output: DC/DC1, 2, 3 will go to maximum duty or current limit; and the LDO pass device will go low resistance. To avoid false trips of the UV monitor, the power good circuit has a 10s glitch filter. Once the output voltage rises above the UV threshold and back into regulation, the fault is cleared and the power good signal goes high.
START-UP SEQUENCE
When power is first applied to the 34700, the internal regulators and bias circuits need to be up and stable before the power on reset (POR) signal is released. The POR waits until the gate drive regulator's voltage, VGREG, has reached about 4V before it allows the rest of the internal blocks to be enabled. Each regulator has an independent enable pin. This allows the user to program the power up sequence to suit the application. As each regulator is turned on, it will execute a soft start ramp of the output voltage. This is done to prevent the output voltage from overshooting the regulation point. Without a soft start ramp, the output voltage will ramp up faster than the control loop can typically respond, resulting in overshoot. As a result, the soft start periods for the switching regulators are longer (3.5ms) than for the linear regulator (0.5ms). The soft start is active each time the regulator is enabled, after a fault retry, or when the IC power is recycled. After a successful start-up sequence, where all the regulators are enabled, no faults have occurred, and the output voltage is in regulation, the power good signal goes
CURRENT LIMIT
A current limit condition for the switching regulators' occurs when the peak current in the high side power MOSFET exceeds the current limit threshold. The switch current is monitored using a sense FET and a comparator. The sense FET acts as a current detecting device by sampling a fraction of the current in the power MOSFET. This sampled current is compared to an internal reference to determine if the regulator is exceeding the current limit or not. If the peak switch current reaches the peak current limit threshold (ISHORT), the regulator will start the cycle by cycle
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current limit operation, the power good signal is pulled low after the 10s glitch filter, and a 10ms current limit timer (tLIM) begins. The regulator will stay in this mode of operation until one of the following occur: * The current is reduced back to normal levels before the current limit timer expires and normal operation is resumed. * The current limit timer expires without regaining normal operation, at which time the regulator turns off. The regulator remains off for a 100ms retry timeout period (tTIMEOUT), after which the regulator will attempt a soft start cycle. * The switch current continues to increase until it exceeds the cycle by cycle current limit by approximately 1A. At this point the regulator shuts down immediately. The regulator remains off for a 100ms retry timeout period (tTIMEOUT), after which the regulator will attempt a soft start cycle.
* The device reaches the thermal shutdown limit (TSD), the regulator turns off.
THERMAL SHUTDOWN
A thermal limit condition occurs when a power device reaches the thermal shutdown threshold (TSD). The temperature of the power MOSFETs in the switching regulators and the LDO are monitored using a thermal sensing transistor located near the power devices. If the temperature of a switcher or an LDO reaches the thermal shutdown threshold, the switcher or LDO regulator will switch off and the PGOOD output would indicate a fault by pulling low. The regulator will stay in this mode of operation until the temperature of the die has decreased by the hysteresis value, and the regulator will attempt a soft start cycle.
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Analog Integrated Circuit Device Data Freescale Semiconductor
VIN 9 to 18V
R1 200 C5 2700pF R4 3.6k C7 1F R5 10k C6 1F R2 18k 4.7k R3 C4 22pF C3 560pF C1 22F C2 22F
VIN1
FB1
AGND
VDDI
COMP1
VOUT1
VOUT1 3.3V
C13 10F D1 B320A BST1 GND2 L2 4.7H SW2 VIN2 EN1 EN2 EN3 COMP2 FB2 EN_LDO FB3 COMP3 C17 .1F BST2 BST3 VIN3 C26 .1F C23 22pF C22 1000pF R11 5.6k R12 24k R14 20k C25 1F C18 1F SW3 LDO_FB GND3 SW1 LDO R15 2.87k SW1 LDO_VIN
C12 C11 10F 10F C14 .1F VIN1
PGOOD
VGREG
Analog Integrated Circuit Device Data Freescale Semiconductor
PGOOD
R6 4.7 C8 1F C10 1F C9 1F L1 4.7H VIN R16 10k
R17 TBD
C15 C16 10F 10F
MC34700
C29 10F
VOUT_LDO 0.9V
TYPICAL APPLICATIONS
Figure 5. Typical Application Diagram
L3 C27 4.7H 10F R7 680 C19 560pF R10 15k R8 15.8k R9 6.19k C20 22pF C21 1000pF C24 R13 1200pF 150
VOUT2 2.5V
C28 10F
R18 TBD
VOUT3 1.25V
TYPICAL APPLICATIONS OPERATIONAL MODES
EN1 EN2 EN3 EN4
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DESIGN CONSIDERATIONS INPUT/OUTPUT CONFIGURATION
The 34700 has independent inputs for each regulator. This allows a high degree of flexibility as far as how the IC can be configured. First, consider what supplies are available in the application, and the input voltage range that each regulator has. Only Buck Converter 1 has a 9V to 18V input voltage range. All the other regulators have a 1.5V to 6V input voltage range. Next, consider the output voltages and currents required, and how best to match them to the 34700. Buck Converter 1 is capable of 2V to 5.25V at 1.5A, while Buck Converters 2 and 3 are capable of 0.7V to 3.6V at 1.25A each. The LDO is capable of 0.7V to 3.6V at a 400mA output. Some sample configurations are show in Figures 6 thru 8. Note that not all combinations are shown, and all the regulators require an input voltage higher than the output voltage.
9.0V to 18V IN Buck Converter 1 2.0V to 5.25V OUT
Buck Converter 2 Buck Converter 3
0.7V to 3.6V OUT
0.7V to 3.6V OUT
LDO
0.7V to 3.6V OUT
Figure 8. Single Input Supply Configuration
INPUT/OUTPUT POWER
Based on the application specifications and the regulator's configuration, the input and output power requirements need to be checked. For the LDO, the input and output powers are calculated:
9.0V to 18V IN
Buck Converter 1
2.0V to 5.25V OUT 1.5A MAX
POUT(LDO) = VOUT x I OUT PIN(LDO) = VIN x I IN I IN = I OUT
For the buck converters, the input and output powers are calculated:
1.5V to 6.0V IN
Buck Converter 2 Buck Converter 3
0.7V to 3.6V OUT 1.25A MAX 0.7V to 3.6V OUT 1.25A MAX
1.5V to 6.0V IN
1.5V to- 6.0V IN
LDO
0.7V to 3.6V OUT 400mA MAX
POUT(BUCK) = VOUT x I OUT PIN(BUCK) = POUT ( BUCK )
Figure 6. General Configuration
9.0V to 18V IN
Buck Converter 1
2.0V to 5.25V OUT
I IN =
PIN(BUCK) VIN
1.5V to 6.0V IN
Buck Converter 2 Buck Converter 3
0.7V to 3.6V OUT
0.7V to 3.6V OUT
LDO
Figure 7. Dual Input Supply Configuration
Where is the estimated efficiency of the buck converters, use 0.85 for the initial estimate. When making the power calculations, be sure to include any input currents from regulators that are connected to the converter as part of the output current. For example, the input currents of Buck Converters 2 and 3 should be added to the system load current of Buck Converter 1 shown in Figure 8. After completing the calculations for all the regulators, check to make sure there are no violations of the power budget - input currents exceeding supply current capabilities, or output currents exceeding the regulator's rating. maximum duty cycle of the buck converters need to be checked against the limits. For Buck Converter 1, there is a minimum limit of 16% and a maximum limit of 68.4%. For
MINIMUM/MAXIMUM DUTY LIMIT
Based on the application specifications, the minimum and
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Buck Converters 2 and 3 there is a maximum limit of 83.6%. The duty cycle for a buck converter is calculated using:
PDISS = (VOUT - VIN ) x I OUT
Since the maximum power dissipation for the LDO is 375mW, the user can determine what the limits are for the LDO's input voltage.
D=
VOUT x100% VIN
This equation works for calculating the minimum duty cycle, however, the above formula does not take into account load currents and losses. A more accurate equation for calculating the maximum duty under load follows:
VOUT + 0.25V VIN VOUT +
0.375 I OUT
D MAX =
VOUT + (R DO + R DC ) x I OUT x 100% VIN(MIN)
CASCADED OPERATION, SEQUENCING, AND LEAKAGE
When the 34700 is configured for cascaded operation, where the output of one regulator powers the input of another regulator (see Figure 8), the startup sequence also needs to be cascaded. The output voltage of the first regulator needs to be up and stable before enabling the downstream regulator, otherwise startup overshoot can occur. Even without being configured for cascaded operation, the user may prefer the cascaded sequence to prevent startup latch-up or race conditions. With the four independent enables provided, the user can program any power up sequence that the application requires. The enable pins can be controlled by a host processor, a programmable logic device, or a power supply sequencer IC. If the application requires a simpler implementation of the cascaded sequence startup, a single enable signal can be used to start the first regulator in the sequence. When the first regulator is near or in regulation, its output is used to enable the next regulator in the sequence. See Figure 9. Note that there is a time delay from when the enable signal is asserted, until when the soft start ramp begins. For Buck Converter 1, the delay is typically 1ms. For Buck Converter 2 and 3, the delay is typically 160s. When sequencing the regulators on, one parameter that must be considered is the leakage specification. Buck Converters 2 and 3 exhibit 400A of leakage current between VIN and the switch node. This results in the output voltage floating up if the load impedance is high. In cases where the output voltage is floating, it is recommended adding a 1K Ohm resistor between the output and ground.
Where RDO is the equivalent dropout resistance of the buck converter and RDC is the DC resistance of the inductor. Check to make sure all the buck converters are within the duty cycle limit. Converters, where the calculated maximum duty cycle exceeds the limit, run the risk of dropping out of regulation under load. Conversely, the maximum duty cycle limit can be used to predict the maximum load current that can be drawn without the output dropping out of regulation.
I OUT(MAX)
D MAX x VIN - VOUT 100% = (R DO + R DC )
LDO DROPOUT AND POWER DISSIPATION
The input of the LDO needs to exceed the output voltage by a minimum of 250mV, in order to maintain regulation. If the input voltage falls below the dropout level, the output voltage will also start to fall and begin to track the input voltage down. However, choosing an input voltage that exceeds the output voltage by a large amount is not recommended either. This is due to increased power dissipation. The linear regulators power dissipation is calculated using:
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ENABLE
EN1
VOUT1
R1 R2
EN2
VOUT2
R3 R4
EN3
VOUT3
R5 R6
LDO_EN LDO
EN1
PGOOD VOUT1 VOUT2 VOUT3 LDO
1ms
3.2ms 3.2ms
3.2ms 0.5ms 0.1ms
t
Figure 9. 34700 Cascade Sequence
SHUTDOWN SEQUENCE
The shutdown sequence is controlled by the enable pins. By pulling the ENABLE pin low or letting it float, the corresponding regulator is disabled. If the application is being controlled by the host processor or programmable logic device, the regulators can be shutdown in any order. Most power supply sequencer ICs shutdown the regulators in the reverse order of their startup. The first regulator that is turned on is the last regulator to be turned off. For the single ENABLE pin sequencer shown in Figure 9, the shutdown order is the same as for startup; the first regulator that is turned on, is the first regulator turned off.
LAYOUT GUIDELINES
The layout of any switching regulator requires careful consideration. First, there are high di/dt signals present, and the traces carrying these signals need to be kept as short and as wide as possible to minimize the trace inductance, and therefore reduce the voltage spikes they can create. To do this, an understanding of the major current carrying loops is important. See Figure 10. These loops, and their associated components, should be placed in such a way as to minimize the loop size to prevent coupling to other parts of the circuit. Also, the current carrying power traces and their associated return traces should run adjacent to one another, to minimize the amount of noise coupling. If sensitive traces must cross the current carrying traces, they should be made perpendicular to one another to reduce field interaction.
Second, small signal components which connect to sensitive nodes need consideration. The critical small signal components are the ones associated with the feedback circuit. The high impedance input of the error amp is especially sensitive to noise, and the feedback and compensation components should be placed as far from the switch node, and as close to the input of the error amplifier as possible. Other critical small signal components include the bypass capacitors for VIN, VGREG, and VDDI. Locate the bypass capacitors as close to the pin as possible. The use of a multi-layer printed circuit board is recommended. Dedicate one layer, usually the layer under the top layer, as a ground plane. Make all critical component ground connections with vias to this layer. Make sure that the power grounds, GND2 and GND3, are connected directly to the ground plane and not routed through the thermal pad or analog ground. Dedicate another layer as a power plane and split this plane into local areas for common voltage nets. The IC input supply (VIN) should be connected through an RC filter to the 9V to 18V input supply, to prevent noise from Buck Regulator 1's power input (VIN1) from injecting switching noise into the analog circuitry. If possible, further isolation can be made by routing a dedicated trace for VIN, and a separate trace for VIN1. In order to effectively transfer heat from the top layer to the ground plane and other layers of the printed circuit board, thermal vias need to be used in the thermal pad design. It is recommended that 5 to 9 vias be spaced evenly and have a finished diameter of 0.3mm.
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VIN1
VIN2 and 3 Loop Curr ent HS ON HS SW2 and 3 Loop Current SD ON LS GND2 and 3 Loop Current LS ON Loop Curr ent HS ON
HS SW1 SD
BUCK CONVERTER 1
BUCK CONVERTER 2 and 3
Figure 10. Current Loops
COMPONENT SELECTION
Setting the Output Voltage For all the regulators, the feedback resistor divider sets the output voltage. See Figure 11 for the feedback and compensation components referred to in the equations. For the buck regulators, choose a value of about 20K for the upper resistor, and calculate the lower resistor using the following equations:
Setting the Enable for Cascade Sequencing For the cascaded startup sequence shown in Figure 9, the resistor divider sets the output voltage level where the next the next regulator in the sequence will start or shutdown. For top resistors R1, R3, and R5, choose a value of 10K, and calculate the value for the bottom resistors R2, R4, and R6, using the following equation:
RBOT = RBOT = VOUT RTOP x VREF VOUT - VREF
0.78 x RTOP 0.95VOUT - 0.78
R = VREF TOP + 1 R BOT
where, VREF = 0.7V For the LDO regulator, choose a value of about 10K for the lower resistor, and calculate the upper resistor using the following equations:
where, VOUT is the value calculated above using standard value resistors. Choose the closest standard resistance values and check the output voltage levels that enable and disable the regulator in sequence, using the following equations, and adjust if necessary:
V RTOP = RBOT OUT - 1 V REF R VOUT = VREF TOP + 1 R BOT
where, VREF = 0.7V Choose the closest standard resistance values, check the output voltage by using the equations above, and adjust the values if necessary.
R + RBOT VOUT ( EN ) = 0.78 TOP RBOT R + RBOT VOUT ( DISABLE ) = 0.61 TOP RBOT

These equations should give an enable of ~95% of VOUT, and a disable of ~75% of VOUT. Catch Diode An external catch diode is required for Buck Converter 1 to provide a return path for the inductor current when the high side switch is off. The catch diode should be located close to the 34700 and connected using short, wide traces. See the Layout Guidelines for more details.
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It is recommended to use a Schottky diode, due to their low forward voltage drop and fast switching speed. This provides the best efficiency and performance, and is especially true when the output voltage is less than 5V. Choose a Schottky with a 2A to 3A average output current rating and a reverse voltage specified for 30V. Inductor The output inductor is sized to meet the output voltage ripple requirements, and to minimize the load transient response time. For continuous conduction mode (CCM) operation, where the inductor does not fully discharge during the switch off time, and assuming an ideal switch and catch diode, the following equation is used:
L = (VIN(MAX) - VOUT )x
VOUT 1 1 x x VIN(MAX) f SW N x I OUT ( MAX )
characteristics, and a suitable voltage rating. As a general rule, choose ceramic capacitors with a X5R, or X7R dielectric and a voltage rating of 1.5 to 2 times the output voltage, but check with the manufacturer for detailed information. For the buck converters, large transient load overshoots and large voltage ripple are caused by insufficient capacitance as well as high equivalent series resistance (ESR) and high equivalent series inductance (ESL) in the capacitor. To meet the application requirements, the output capacitor must be specified with ample capacitance and low ESR and ESL. To deal with overshoot, where the output voltage overshoots its regulated value when a full load is removed from the output, the output capacitor must be large enough to prevent the energy stored in the inductor from causing the voltage to spike above the specified maximum output voltage. The amount of capacitance required can be estimated using the following equation:
where, fSW is the switching frequency and N is the ripple current to output current ratio. A high ripple current to output current ratio gives improved load transient response, but also increases output ripple, and results in lower efficiency. A value of 0.3 to 0.4 for N represents a good trade off between efficiency, ripple, and load transient response. After calculating a value for the inductor, choose the closest standard value and then determine the ripple current and peak current using the following equations:
C OUT =
L(I PEAK ) (V + VOUT )2 - VOUT 2
2
where, V is the maximum output voltage overshoot. Allow a 20% capacitance tolerance and choose the closest standard value. The ESR of the output capacitor also contributes to the transient overshoot. The maximum ESR can be estimated using the equation:
I L =
(V
IN(MAX)
- VOUT ) I L 2
L
x
VOUT 1 x VIN(MAX) f SW
C ESR =
V I TRANSIENT
I PEAK = I OUT(MAX) +
The peak inductor current determines the required saturation current rating of the inductor. Choose an inductor with a saturation current rating that's large enough to compensate for circuit tolerances. The minimum acceptable margin for this purpose is at least 20% above the calculated rating. To minimize copper losses, choose an inductor with the lowest possible DCR. As a general rule of thumb, look for a DCR of approximately 5mOhms per H of inductance. Output Capacitor The output capacitor is required to minimize the voltage overshoot and undershoot in response to load transients, and to reduce the ripple present at the output of a buck regulator. The same holds true for the linear regulator. For the LDO, a 10F, low ESR capacitor is required as the output capacitor. Smaller values may result in instability. Make sure the capacitor has good temperature
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where, ITRANSIENT is the magnitude of the load transient, and V is the maximum output voltage overshoot. The ESR of the output capacitor usually dominates the output voltage ripple. The maximum ESR can be calculated using the equation:
C ESR =
VRIPPLE I L
where, VRIPPLE is the specified ripple voltage allowed. Note that most capacitor vendors do not specify the ESL of the capacitor and board layout also contribute to the ripple and overshoot. Consult the manufacturer for more information on the characteristics and selection of output capacitors. Use these calculations as a design guideline. After selecting the output capacitors, make adjustments based on actual test results.
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Input Capacitor Generally, a mix of bypass capacitors is used for the input supply. Use a small ceramic capacitor for high frequency decoupling, and bulk capacitors to supply the surge of current required each time the high side MOSFET turns on. Place the small ceramic capacitor close to the power input pins. For reliable operation, select the bulk input capacitors with voltage and RMS ripple current ratings above the maximum input voltage, and the largest RMS current required by the application. As a general guideline, the capacitor's voltage rating should be around 1.5 times the maximum input voltage, but the manufacturer's de-rating information should be followed. The RMS ripple current rating that the bulk input capacitors require can be estimated by the following equation:
Figure 11. The Type III network utilizes two zeroes to give a phase boost of 180. This phase boost is necessary to counteract the double pole of the output LC filter.
C2
Cff
Rff
RTOP CCOMP
COM P
RCOMP
FB
EA
RBOT VREF 34700
+
I IN ( RMS ) = I OUT D - D 2
where D = VOUT/VIN. The worst case occurs when VIN = 2 x VOUT, yielding a worst case ripple current of IIN(RMS) = IOUT/2. The bulk input capacitance required for a buck converter depends on the impedance of the input supply. For common laboratory supplies, 10F to 20F of capacitance per ampere of input ripple current is usually sufficient. Use this general guideline as a starting point and adjust the input capacitance based on actual test results. Tantalum capacitors can be used as input capacitors, but proper de-rating must be used or they can fail "short" and present a fire hazard. Ceramic capacitors and aluminum electrolytic capacitors don't have this failure mechanism, making them a preferred choice. However, ceramic capacitors can exhibit piezo effect and emit an audible buzz. Polymer capacitors do not have this audible noise problem, but they can also fail "short". However, polymer capacitors are much more robust than tantalums, and therefore are suitable as input capacitors. Consult the manufacturer for more information on the use and de-rating of capacitors. Bootstrap Capacitor The external bootstrap capacitor is part of a charge pump circuit which is used to drive the gate of the high side NMOSFET. This capacitor develops a floating voltage supply which is referenced to the switch node (SW) or the source of the high side MOSFET. The bootstrap capacitor is charged every cycle, when the low side MOSFET or the catch diode conducts, to a voltage of about VGREG. To turn the high side switch on, the bootstrap capacitor needs to be large enough to charge the gate-source capacitance of the N-MOSFET without a significant drop in voltage. For the 34700 the bootstrap capacitor should be 0.1F. Compensation The voltage mode buck converters used in the 34700 require a Type III compensation network as shown in
Figure 11. Type III Compensation Network The closed loop transfer function is comprised of the modulator, the filter, and the compensation transfer functions. Before we can determine the compensation we need to first calculate the gains and break frequencies of the modulator and filter.
G MOD =
D MAX x VIN VRAMP
where, GMOD is the modulator gain, and DMAX and VRAMP are given in the electrical table.
f LC =
1 2 L x C
where, fLC is the location of the LC filter double pole.
f ESR =
1 2 x C x ESR
where, fESR is the location of the ESR zero, and ESR is the equivalent series resistance of the output capacitors. As shown in Figure 11, the compensation network consists of the error amplifier (internal to the 34700), and the external resistors and capacitors. If designed properly, the compensation network will yield a closed loop transfer function with a high crossover (0dB) frequency, and adequate phase margin to be stable. Use the following steps to calculate the compensation components. 1. Using the value for RTOP and RBOT, selected in the Setting the Output Voltage section, calculate the value
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TYPICAL APPLICATIONS OPERATIONAL MODES
of RCOMP for the desired converter bandwidth, f0. Typically f0 is chosen to be 1/10th of the switching frequency.
C2 =
C COMP (2 x R COMP x CCOMP x f ESR ) - 1
R COMP =
VRAMP x R TOP x f 0 D MAX x VIN x f LC
4. Calculate the value of Rff and Cff, to place a zero (fZ2) at the LC double pole frequency, and a pole (fP2) at half the switching frequency.
This will set the high frequency gain of the error amplifier (RCOMP/RTOP), and shift the open loop gain up to give the desired bandwidth. 2. Using the value for RCOMP, calculate the value of CCOMP, to place a zero, to cancel one of the double poles. This zero (fZ1) is placed at a fraction of the LC double pole frequency.
R ff =
R TOP f SW 2 x f -1 LC 1 x R ff x f SW
C ff =
C COMP =
1 2 x R COMP x K LC x f LC
where, KLC is the fraction of the LC filter frequency = fZ1/fLC. Typical values for KLC are 0.2 to 0.7, but begin with 0.5. 3. Using the values of RCOMP and CCOMP, calculate the value of C2 to place a pole (fP1) at the ESR zero frequency. Note that if ceramic capacitors are used for the output capacitors, the ESR zero will be at a very high frequency, making the calculated value of C2 very small. If this is the case, C2 may not be needed, saving a component and space.
Choose the closest standard value for the compensation components. Although precision components are not required, do not use poor quality components that have large tolerances over-temperature. As a double check, it is recommended to use a mathematical model to plot the closed loop response. Check that the closed loop gain is within the error amplifier's open loop gain, and there is enough phase margin, and make adjustments as necessary. A stable control loop has a gain crossing with close to -20dB/decade, and a phase margin of at least 45. The following equations describe the frequency response of the modulator, feedback compensation, and the closed loop.
G MOD (f) = H COMP (f) =
D MAX x VIN 1 + s(f) ESR C VRAMP 1 + s(f) (ESR + DCR ) C + s 2 (f) L C 1 + s(f) R COMP C COMP s(f) R TOP (C COMP + C 2 )
1 + s(f) (R TOP + R ff ) C ff C C 1 + s(f) R ff C ff 1 + s(f) R COMP COMP 2 C COMP + C 2
G CL (f) = G MOD (f) H COMP (f) where, s(f) = j 2 f
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A more intuitive representation of the mathematical model, is an asymptotic bode plot of the buck converter's gain versus frequency, as shown in Figure 12. Use of the previous steps should result in a compensation gain similar to the one shown in the bode plot. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at fP1 or fP2, whichever is greater, against the capabilities of the error amplifier. For reference, the equations for the compensation break frequencies are given.
f Z1 = f P1 =
1 2 x R COMP x C COMP 1 C x C2 2 x R COMP x COMP C COMP + C 2 1 2 x (R TOP + R ff )x C ff 1 2 x R ff x C ff
f Z2 = f P2 =
fZ1 fZ2 fP1
GAIN (dB)
fP2
ERROR AMP OPEN LOOP
0
HCOMP
GCL
GMOD
fLC
fESR
f0
FREQUENCY (LOG Hz)
Figure 12. Bode Plot of the Buck Converter
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
EP SUFFIX (Pb FREE) 32-PIN 98ASA10800D REVISION D
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PACKAGING PACKAGE DIMENSIONS
EP SUFFIX (Pb FREE) 32-PIN 98ASA10800D REVISION D
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PACKAGING PACKAGE DIMENSIONS
EP SUFFIX (Pb FREE) 32-PIN 98ASA10800D REVISION D
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REVISION HISTORY
REVISION HISTORY
REVISION 1.0 2.0 3.0 4
DATE 4/2008 4/2008 5/2008 6/2008
DESCRIPTION OF CHANGES * * * * Initial release Changed the 98A package drawing from 98ARE10566D to 98ASA10800D Corrected error on MC34700 Simplified Application Diagram on page 1 Changed category from "Advance Information" to "Technical Data"
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REVISION HISTORY
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MC34700 Rev. 4 6/2008

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